#this is a test zero bias MACRO 
# note: the array is read out 10 times,
#the bias is zeroed, restored and flushed
#ten times, then readout 10 times again
#2 sets of these sequences are done for itime=1sec,
#10sec and 30 sec.
#GResetsNS = usually 20000
#VDET voltage
# SetDac 1 10 -3.35
#VDDUC=-3.75
#SetDac 1 11 -3.75
#VGGCL voltage
#SetDac 1 0 -3.0
#was SetDac 1 0 -3.15
#BGreset =  20usec
#BGR.ns 40000
#reset delay before int
#BGR.min.ms 250
#bgr.ms 2000
#Gflt 3.454
#Osf 0.1 Stop
#Slit Mirror
#Rot 0
Object onaka_zb_sat_test MACRO
SlowCnt 12
autosave on
# 1
GFlt Blank
m.wait 30
isready
cycles 5
Comment prefluxsamples 1_prezero
itime 90
go
isready
GFlt 3.454
m.wait 30
isready
cycles 5
Comment fluxsamples 1_prezero
itime 90
go
isready
GFlt Blank
m.wait 30
isready
cycles 1
#ZERO BIAS
#VDET voltage
SetDac 1 10 -3.75
#VDDUC=-3.75
SetDac 1 11 -3.75
#VGGCL voltage
SetDac 1 0 -3.75
isready
m.wait 5
#RESTORE 0.4Vbias
#VDET voltage
SetDac 1 10 -3.35
#VDDUC=-3.75
SetDac 1 11 -3.75
#VGGCL voltage
SetDac 1 0 -3.15
isready
Comment FLUSH frame
Slowcnt 1
Coadd 500
Itime 0.01
go
isready
m.wait 40
Slowcnt 12
Coadd 1
isready
#preread to set level
Comment bias drift correction
Itime 10
go
isready
cycles 5
Comment blanksamples 1_postzero
itime 90
go
isready
cycles 1
autosave off